I am new to hardware counter measurements on intel. I want to measure L3 misses to local and remote DRAM on Intel Ivy bridge Model 62(Intel(R) Xeon(R) CPU E7-4860):
I need to understand the difference between OFFCORE_RESPONSE_0 and OFFCORE_RESPONSE_1 as both have the same sub-fields. Can I use either of these two to measure L3_LOCAL_MISSES and L3_REMOTE_MISSES? I am using PAPI low-level interface to add these two events and measure their counters for a section of my code. I have read/write access to MSR registers. Do I need to set up any lower level bits or anything related to offcore request?